A microcontroller is a single-chip microcomputer that integrates the main parts of a microcomputer on a single chip. Microcontrollers were born in the mid-1970s, and after more than 20 years of development, their cost is getting lower and lower, while their performance is getting more and more powerful, which makes their applications have become ubiquitous in various fields. For example, motor control, barcode readers/scanners, consumer electronics, gaming devices, telephones, HVAC, building security and access control, industrial control and automation and white goods (washing machines, microwave ovens), etc.
Microcontroller development history
Intel, as the first company to introduce microprocessors, is also the first company to introduce microcontrollers. Following the launch of the MCS-48 in 1976, it launched the MCS-51 in 1980, laying a good foundation for the development of a new generation of microcontrollers with good compatibility. After the 8051 technology became open, companies such as Philips, Atmel, Dallas and Siemens have launched microcontrollers based on the 80C5l core (CMC)S version of the 805l). These distinctive products can meet the needs of a large number of embedded applications. The development of microcontrollers based on the 80C51 core has not stopped, for example, the DS89C430 series microcontrollers from Maxim/Dallas now have 12 times the single-cycle instruction speed of the 805l.
CISC architecture-based microcontrollers include, in addition to the 80C51, the 68HC series of microcontrollers provided by Motorola, which is also a family of 8-bit microcontrollers for a large number of applications.
RISC-based microcontrollers include Microchip’s PIC series of 8-bit microcontrollers. Among the 16-bit RISC architecture microcontrollers, Maxim’s MAXQ series microcontrollers are ideal for many applications requiring high-precision mixed-signal processing as well as portable systems and battery-powered systems due to their high performance, low power consumption and excellent code execution efficiency.
Microcontroller Unit (MCU) can be classified in different ways: according to the data bus width can be divided into 8-bit, 16-bit and 32-bit machines; according to the memory structure can be divided into Harvard structure and Von Neumann structure; according to the category of embedded program memory can be divided into OTP, mask, EPROM/ EEPROM and Flash memory; according to the instruction structure, it can be divided into CISC (Complex Instruction Set Computer) and RISC (Reduced Instruction Set Computer) microcontrollers.
CISC microcontrollers based on 8051 cores
So far, MCS-51 has become the slowest running series among 8-bit machines. Now Dallas has introduced the DS89C430 family, which achieves the highest throughput rate of the 8051 family while maintaining compatibility with the 80C51 pinout and instruction set at only one clock per machine cycle. In general, existing 8051-based applications can be written directly to the DS89C430 without modification. In addition to this, the DS89C430 introduces new features in many other areas that provide more flexibility for specific applications. The following describes the functions and features that make the DS89C430 different from the 8051.
On-chip program memory and applications
The on-chip program memory is logically divided into pairs of 8 KB, 16 KB or 32 KB flash memory cells to support in-application programming. This allows the device to modify the program memory under the control of the application software and the application system to perform its primary function while completing an online software upgrade. 64 B encrypted arrays are integrated into the DS89C430, allowing the user to view data in encrypted form for program code verification.
The device supports in-system programming via the RS-232 serial port. In-system programming activates the bootloader by setting one or more external pins of the device to a specific state. Once the device is booted, execution of the load program, which resides in a dedicated ROM inside the device, begins. Once a carriage return symbol is received, the serial port performs an automatic baud rate function and synchronizes with the host’s baud rate. The physical connection for programming in the system is shown in Figure 1. The simple bootloader interface allows several methods to be used to implement communication between the PC and the target microcontroller
communication between the PC and the target microcontroller. The simplest method is to use Dallas’ Microcontroller Toolkit (MTK) software. It has highly front-end features that simplify target configuration, uploading and downloading code, and special function configuration tasks.
The dual data pointer 8051 microcontroller is used to access the off-chip data space with the MOVX instruction, and the entire 64 KB of off-chip data memory can be accessed with the MOVX@DPTR instruction. The DS89C430 has dual data pointers DPTR0 and DPTRl, so software can use one pointer to load the source address and the other to load the destination address. DPTR0 has the same SFR address as 805l (82H and 83H), so No source code changes are required when using this pointer, and DPTRl is located at addresses 84H and 85H. All operations related to the data pointer use the active data pointer, which is selected by the control bit SEL. Each pointer also has Each pointer also has a control bit that determines whether the INCDPTR operation increments or decrements the data pointer value.
When copying blocks of data, the double data pointer saves a lot of code compared to using a single data pointer. The user converts the active data pointer by converting the SEL bit, one way of doing this can be done by executing the INCDPS instruction. To increase speed and efficiency while saving code, the DS89C430 includes a conversion select bit (TSL) to determine if the hardware automatically converts the SEL bit when the MOVX instruction is executed, which eliminates the need for the INCDPS instruction and further increases This eliminates the need for the INCDPS instruction and further increases the speed of operation.
Large data block copies require byte-by-byte addressing of the data space by source and destination pointers, which are traditionally augmented by using the INCDPTR instruction. To further increase the data transfer rate, an automatic increment/decrement control bit (AID) is introduced to determine whether the active pointer value will be automatically incremented or decremented when the MOVX instruction is executed. Table l shows the speed comparison between the DS80C320 and DS89C430 when performing 64B data block transfers for various cases. As can be seen in Table l, the operation speed is greatly improved by using dual data pointers.
Power management and clock division control
The power consumption of the CMOS circuit consists of two main components: the static power consumption caused by the continuous leakage current and the dynamic power consumption caused by the switching current required to charge and discharge the load capacitor. The dynamic power consumption is the main part of the overall power consumption, and this power consumption (PD) can be calculated from the load capacitance (CL), the supply voltage (VDD), and the operating frequency (f), i.e., PD = CL × VDD2 × f.
For a specific application, the capacitance and supply voltage are relatively fixed, while the processing speed of the processor may be different at different moments, so the operating frequency can be adjusted according to different needs, so as to achieve the requirement of reducing power consumption without affecting the system performance.
The DS89C430 supports three low-power saving modes.
① System clock dividing control: Allows the microcontroller to continue working using an internally divided clock source to save power. The clock division control bit is set by software to set the operating rate to 1024 oscillator cycles per machine cycle.
② Idle mode: Holds the program counter in a static manner and hangs the processor. In this mode, the processor does not fetch instructions nor execute them. All resources are saved except for the peripheral interface clock which remains active and the timer, watchdog, serial and power monitoring functions which remain operational. The processor is able to exit the idle mode using the allowed interrupt sources.
(iii) Shutdown mode: All circuitry inside the processor is disabled. All on-chip clocks, timers, and serial communications are stopped and the processor does not execute any instructions. The processor is able to exit the shutdown mode by using any of the six external interrupts.
RISC architecture-based microcontroller
The MAXQ2000 microcontroller is a 16-bit microcontroller based on the RISC architecture from Maxino/Dallas. Understanding some of the architectural features of this microcontroller will allow us to better understand the latest trends and technical features of RISC architecture microcontrollers, thus providing us with a more desirable option for building new systems. MAXQ2000 instruction read and execution operations are completed in one cycle without pipelining operations, because instructions contain both opcodes and data. The letter Q indicates that an important feature of this microcontroller is that it is “quiet” and that the MAXQ architecture reduces noise through intelligent clock management. This means that MAXQ only provides clocks to those circuits that need to use them, which reduces power consumption and provides the quietest environment for the integration of analog circuits. It includes a liquid crystal display (LCD) interface that can drive up to 100 or 132 segments (both versions). This microcontroller is a leader in power consumption metrics and MIPS/MHz code efficiency among similar microcontrollers. The main features of the MAXQ2000 are described below.
Microcontroller Instruction Set
The instruction set consists of 23 fixed-length, 16-bit instructions that operate on registers and memory. The instruction set is highly orthogonal, allowing arithmetic and logic operations to use accumulators and any registers. Special function registers control peripheral devices and are subdivided into register modules. The product family structure is modular, so new devices and modules can continue to use the code developed for existing products. The structure is transfer-triggered, which means that reads or writes to a register location have additional effects. These additional actions form the basis for the high-level opcodes defined by the assembler, such as ADDC, OR and JUMP.
The MAXQ2000 has 32KB of Flash memory, lKB of RAM, 4KB of internal ROM memory blocks, and 16 levels of stacked memory. The memory is configured as a Harvard structure by default, with separate address spaces for program and data memory, and can be enabled for Vorl Ncumann memory configuration mode, which places fixed-use ROM, code, and data memory into a contiguous memory map. This is suitable for applications that require dynamic program modification or special memory configurations. Flash program memory can be password protected by a 16-word key, thus preventing unauthorized access to the program memory. It also has three data pointers to support efficient and fast data processing.
The fixed-use ROM consists of subroutines that can be called from the application software (default starting address is 8000H). These include: in-system programming (bootloader) via JTAG or UART interface; in-circuit debugger; test programs (internal memory test, memory load, etc.); and user-callable programs for in-application flash programming and quick lookup tables. Regardless of the reset method, the program is run from the fixed-use ROM, and the M software determines whether the program jumps immediately to location 8000H, to the start of the user application code, or to a specific application subroutine as mentioned above. The user has access to the programs in the fixed-use ROM and they can be called by the application software.
Microcontroller Register Set
Most of the device’s functions are controlled by register groups. These registers provide the workspace for memory operations and configure and address peripheral registers on the device. The registers are divided into two main categories: system registers and peripheral registers. The public register group, also called system registers, includes ALUs, accumulator registers, data pointers, stack pointers, etc. Peripheral registers define additional functionality that may be included in different products based on the MAXQ architecture．
Microcontroller Power Management
The MAXQ2000 also provides advanced power management features that allow the processing speed to be dynamically set according to the different performance requirements of the system at different moments, thus significantly reducing power consumption. A software-selected divider function allows you to choose whether the system clock period is l, 2, 4, or 8 amplitude periods. To further reduce power consumption, there are three other low-power modes, 256 dividers, 32 kH. and shutdown mode.
The MAXQ architecture uses a single interrupt vector (IV) and a single interrupt service program (ISR) design. The interrupt flag must be cleared within the user interrupt program to avoid repeated interrupts triggered by the same interrupt source. When an enabled interrupt is detected, software jumps to a user-programmable interrupt vector location.
Once software control is transferred to the ISR, the Interrupt Identification Register (IIR) can be used to determine whether the interrupt source is a system register or a peripheral register. The specific module can then be queried to determine the specific interrupt source and take the appropriate action. Since the interrupt source is identified by user software, the user can establish a unique interrupt prioritization scheme for each application.
Microcontroller Hardware Multipliers
The integrated hardware multiplier module performs high-speed multiplication, multiplication square and accumulation operations and is capable of completing a 16-bit x 16-bit multiplication and accumulation operation in a single cycle. The hardware multiplier consists of two] 6-bit parallel load operand registers (MA, MB) and an accumulator. The load registers are capable of automatically starting the operation, thus saving the time for repeated calculations. The accumulation function of the hardware multiplier is a base unit in digital filtering, signal processing, and PII) control systems, which makes the MAXQ2000 competent for applications that require a large number of mathematical operations.
The Harvard architecture is a memory structure that separates program instruction storage from data storage. The central processor first goes to the program instruction memory to read the program instruction content, decodes it to get the data address, then reads the data from the corresponding data memory and performs the next operation (usually execution). The program instruction memory and data memory are separated, which can make the instruction and data have different data widths, such as Microchip’s PIC16 chip, where the program instruction is 14 bits wide and the data is 8 bits wide.
Microprocessors with Harvard architecture usually have high execution efficiency. Its program instructions and data instructions are organized and stored separately, and the next instruction can be read in advance during execution. At present, there are many central processors and microcontrollers using Harvard structure, besides the PIC series chips of Microchip mentioned above, there are MC68 series of Motorola, Z8 series of Zilog, AVR series of ATMEL and ARM9, ARM10 and ARM11 of Anmou, 51 microcontrollers also belong to Harvard structure.
The von Neumann architecture, also known as the Princeton architecture, is a memory structure that combines program instruction memory and data memory together. Program instruction memory addresses and data memory addresses point to different physical locations in the same memory, so program instructions and data are the same width, e.g., Intel’s 8086 central processing unit is 16 bits wide for both program instructions and data.
There are many central processors and microcontrollers that use the von Neumann architecture. In addition to the above-mentioned Intel’s 8086, other central processors of Intel, ARM7 of Anmou, and MIPS processor of MIPS also use the von Neumann structure.
Microcontroller development prospects
Through the above comparative analysis of the two types of microcontrollers based on CISC． and RISC architecture, many common features will be found, such as security features, peripherals, power management and in-system programming. Obviously. They are all added features to meet the common requirements of specific applications. The biggest difference between the two is the difference in instruction structure. mcs 5l has 50 basic instructions, if the accumulation of different addressing methods, the total number of instructions lll, corresponding to the machine instructions have single-byte, double-byte and triple-byte instructions ~ 68H (: 05 has 62 basic instructions, plus a variety of addressing methods, the final instructions up to 210, also divided into single-byte, double-byte and triple-byte instructions. In comparison, RIS (: all instructions of the microcontroller are composed of a number of simple, equal-length instructions. Streamlined instructions allow the microcontroller’s wiring to be optimized as much as possible and the hardware structure to be simpler so that lower cost and power consumption can be achieved, although more instructions may be needed to accomplish the same work. Therefore, there is no absolute advantage between the two trade-offs, only that the choice is based on the different needs and focus of the application.
The microprocessor is one of the great technological innovations of the 20th century, and the resulting microcontroller combines the microprocessor and peripherals in one package, opening up new horizons for a variety of applications and will continue to play an irreplaceable role.